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Agilent HFBR-5730L/LP Small Form Factor Pluggable Optical Transceiver for Fibre Channel (1.0625 GBd)
Data Sheet
Applications * Mass storage system I/O * Computer system I/O * High-speed peripheral interface * High-speed switching systems * Host adapter I/O * RAID cabinets Description The HFBR-5730L optical transceiver from Agilent Technologies offers maximum flexibility to Fibre Channel designers, manufacturers, and system integrators to implement a range of solutions for multimode Fibre Channel applications. In order to provide a wide range of system level performance, this product is fully compliant with all equipment meeting the new Fibre Channel FC-PI 100-M5-SN-I and 100-M6-SN-I 1.0625 GBd specifications, and is also compliant with the older Fibre Channel FC-PH-2 100-M5-SN-I, and the FC-PH-2 100-M6-SN-I 1.0625 GBd specifications. Module Package The transceiver meets the Small Form Pluggable (SFP) industry standard package utilizing an integral LC-Duplex optical interface connector. The hot-pluggable capability of the SFP package allows the module to be installed at any time - even with the host system operating and on-line. This allows for system configuration changes or maintenance without system down time. Features * Compliant with 1.0625 GBd Fibre Channel FC-1 standard - FC-PI 100-M5-SN-I for 50/120 m multimode cables - FC-PI 100-M6-SN-I for 62.5/125 m multimode cables * Compliant with Fibre Channel FC-PH-2 standard * Industry standard Small Form Pluggable (SFP) package * LC-Duplex connector optical interface * Link lengths at 1.0625 GBd: 0.5 to 500 m - 50/125 m MMF 0.5 to 300 m - 62.5/125 m MMF * Reliable 850 nm Vertical Cavity Surface Emitting Laser (VCSEL) source technology * Laser AEL Class I (eye safe) per: US 21 CFR (J) EN 60825-1 (+ All) * Single +3.3 V power supply operation * Hot pluggable * Delatch options: - HFBR-5730L standard delatch - HFBR-5730LP bail-wire pull delatch Related Products * HFBR-5720L: 2.125/1.0625 GBd 3.3 V SFP Fibre Channel Transceiver for FC-PI-2 * HFBR-5921L: 2.125/1.0625 GBd 3.3 V SFF PTH Fibre Channel Transceiver for FC-PI-2 * HFBR-5710L: 850 nm 1.25 GBd 3.3 V SFP Gigabit Ethernet Transceiver * HFBR-53A3VEM/VFM: 850 nm 1.0625 GBd 3 V, 1 x 9 Fibre Channel Transceiver for FC-PH-2 * HFBR-5602: 850 nm 5 V Gigabit Interface Converter (GBIC) for Fibre Channel FC-PH-2 for FC-PH2 * HDMP-2630/2631 2.125/1.0625 GBd TRx family of SerDes IC * HDMP-1687 1.0625 GBd Quad SerDes IC
HFBR-5730L BLOCK DIAGRAM RECEIVER
AMPLIFICATION & QUANTIZATION
ELECTRICAL INTERFACE
RD+ (RECEIVE DATA) RD- (RECEIVE DATA) LOSS OF SIGNAL
LIGHT FROM FIBER
PHOTO-DETECTOR
OPTICAL INTERFACE TRANSMITTER
LASER DRIVER & SAFETY CIRCUITRY Tx_DISABLE TD+ (TRANSMIT DATA) TD- (TRANSMIT DATA) Tx_FAULT
LIGHT TO FIBER
VCSEL
MOD-DEF2 EEPROM MOD-DEF1 MOD-DEF0
Figure 1. Transceiver functional diagram.
The HFBR-5730L uses a reliable 850 nm VCSEL source and requires a 3.3 V DC power supply for optimal system design. Module Diagrams Figure 1 illustrates the major functional components of the HFBR-5730L. The connection diagram of the module is shown in Figure 2. Figure 7 depicts the external configuration and dimensions of the module. Installation The HFBR-5730L can be installed in or removed from any MultiSource Agreement (MSA) compliant Small Form Pluggable port regardless of whether the host equipment is operating or not. The module is simply inserted, electrical-interface first, under finger-pressure. Controlled hot-plugging is ensured by design and by 3-stage pin sequencing at the electrical interface. The module housing makes initial contact with the host board EMI shield mitigating potential damage due to Electro-Static Discharge (ESD). The 3-stage pin contact sequencing involves (1) Ground, (2) Power, and then (3) Signal
pins, making contact with the host board surface mount connector in that order. This printed circuit board card-edge connector is depicted in Figure 2. Serial Identification (EEPROM) The HFBR-5730L complies with an industry standard MultiSource Agreement that defines the serial
identification protocol. This protocol uses the 2-wire serial CMOS E2PROM protocol of the ATMEL AT24C01A or equivalent. The contents of the HFBR-5730L serial ID memory are defined in Table 10 as specified in the SFP MSA.
20 19 18 17 16 15 14 13 12 11
VEET TD- TD+ VEET VCCT VCCR VEER RD+ RD- VEER TOP OF BOARD
1 2 3 4 5 6 7 8 9 10
VEET Tx FAULT Tx DISABLE MOD-DEF(2) MOD-DEF(1) MOD-DEF(0) RATE SELECT LOS VEER VEER
BOTTOM OF BOARD (AS VIEWED THROUGH TOP OF BOARD)
Figure 2. Connection diagram of module printed circuit board.
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Transmitter Section The transmitter section includes the transmitter optical subassembly (TOSA) and laser driver circuitry. The TOSA, containing an 850 nm VCSEL (Vertical Cavity Surface Emitting Laser) light source, is located at the optical interface and mates with the LC optical connector. The TOSA is driven by a custom silicon IC, which converts differential logic signals into an analog laser diode drive current. This Tx driver circuit regulates the optical power at a constant level provided the data pattern is valid 8B/10B DC balanced code.
Tx Disable
laser operation. A transmitter fault condition can be caused by deviations from the recommended module operating conditions or by violation of eye safety conditions. A transient fault can be cleared by cycling the Tx Disable control input.
Eye Safety Circuit
For an optical transmitter device to be eye-safe in the event of a single fault failure, the transmitter will either maintain normal, eye-safe operation or be disabled. In the event of an eye-safety fault, the VCSEL will be disabled. Receiver Section The receiver section includes the receiver optical subassembly (ROSA) and amplification/quantization circuitry. The ROSA, containing a PIN photodiode and custom transimpedance preamplifier, is located at the optical interface and mates with the LC optical connector. The ROSA is mated to a custom IC that provides post-amplification and quantization. This circuit also includes a loss of signal (LOS) detection circuit which provides an open collector logic high output in the absence of a usable input optical signal level.
Loss of Signal
input signal to the receiver does not meet the minimum detectable level for Fibre Channel compliant signals. When LOS is high it indicates loss of signal. When LOS is low it indicates normal operation. The Loss Of Signal thresholds are set to indicate a definite optical fault has occurred (e.g., disconnected or broken fiber connection to receiver, failed transmitter).
Functional Data I/O
The HFBR-5730L accepts a transmit disable control signal input which shuts down the transmitter. A high signal implements this function while a low signal allows normal laser operation. In the event of a fault (e.g., eye safety circuit activated), cycling this control signal resets the module as depicted in Figure 6. The Tx Disable control should be actuated upon initialization of the module.
Tx Fault
Agilent's HFBR-5730L fiber-optic transceiver is designed to accept industry standard differential signals. In order to reduce the number of passive components required on the customer's board, Agilent has included the functionality of the transmitter bias resistors and coupling capacitors within the fiber optic module. The transceiver is compatible with an "AC-coupled" configuration and is internally terminated. Figure 1 depicts the functional diagram of the HFBR 5730L. Caution should be taken to account for the proper interconnection between the supporting physical layer integrated circuits and the HFBR-5730L. Figure 4 illustrates the recommended interface circuit. Several MSA compliant control data signals are implemented in the module and are depicted in Figure 6.
The HFBR-5730L module features a transmit fault control signal output which when high indicates a laser transmit fault has occurred and when low indicates normal
The Loss of Signal (LOS) output signal indicates that the optical
NORMALIZED AMPLITUDE
1.3 1.0 0.8 0.5 0.2 0 -0.2 0 x1 0.4 0.6 1-x1 1.0
NORMALIZED TIME (IN UI)
Figure 3. Transmitter eye mask diagram and typical transmitter eye.
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Application Support
Evaluation Kit
To help you in your preliminary transceiver evaluation, Agilent offers a 1.0625 GBd Fibre Channel evaluation board. This board will allow testing of the fiberoptic VCSEL transceiver. Please contact your local Field Sales representative and request part number HFBR-0571.
Reference Designs
production environments. The second condition is static discharges to the exterior of the host equipment chassis after installation. To the extent that the duplex LC optical interface is exposed to the outside of the host equipment chassis, it may be subject to system-level ESD requirements. The ESD performance of the HFBR-5730L exceeds typical industry standards.
Immunity
Flammability
The HFBR-5730L VCSEL transceiver housing is made of metal and high strength, heat resistant, chemically resistant, and UL 94V-0 flame retardant plastic. Caution There are no user serviceable parts nor any maintenance required for the HFBR-5730L. Tampering with or modifying the performance of the HFBR-5730L will result in voided product warranty. It may also result in improper operation of the HFBR-5730L circuitry, and possible overstress of the laser source. Device degradation or product failure may result. Connection of the HFBR-5730L to a non-approved optical source, operating above the recommended absolute maximum conditions or operating the HFBR-5730L in a manner inconsistent with its design and function may result in hazardous radiation exposure and may be considered an act of modifying or manufacturing a laser product. The person(s) performing such an act is required by law to re-certify and re-identify the laser product under the provisions of U.S. 21 CFR (Subchapter J) and the TUV. Ordering Information Please contact your local field sales engineer or one of Agilent Technologies franchised distributors for ordering information. For technical information regarding this product, including the MSA, please visit Agilent Technologies Semiconductors Products Website at www.agilent.com/view/fiber. Use the quick search feature to search for this part number. You may also contact Agilent Technologies Semiconductor Products Customer Response Center at 1-800-235-0312.
Reference designs for the HFBR5730L fiber-optic transceiver and the HDMP-1687 physical layer IC are available to assist the equipment designer. Figure 4 depicts a typical application configuration, while Figure 5 depicts the MSA power supply filter circuit design. All artwork is available at the Agilent electronic bulletin board. Please contact your local Field Sales engineer for more information regarding application tools. Regulatory Compliance See Table 1 for transceiver Regulatory Compliance performance. The overall equipment design will determine the certification level. The transceiver performance is offered as a figure of merit to assist the designer.
Electrostatic Discharge (ESD)
Equipment hosting the HFBR5730L modules will be subjected to radio-frequency electromagnetic fields in some environments. The transceivers have good immunity to such fields due to their shielded design.
Electromagnetic Interference (EMI)
Most equipment designs utilizing these high-speed transceivers from Agilent Technologies will be required to meet the requirements of FCC in the United States, CENELEC EN55022 (CISPR 22) in Europe and VCCI in Japan. The metal housing and shielded design of the HFBR-5730L minimize the EMI challenge facing the host equipment designer. These transceivers provide superior EMI performance. This greatly assists the designer in the management of the overall system EMI performance.
Eye Safety
There are two conditions in which immunity to ESD damage is important. Table 1 documents our immunity to both of these conditions. The first condition is during handling of the transceiver prior to insertion into the transceiver port. To protect the transceiver, it is important to use normal ESD handling precautions. These precautions include using grounded wrist straps, work benches, and floor mats in ESD controlled areas. The ESD sensitivity of the HFBR-5730L is compatible with typical industry
These 850 nm VCSEL-based transceivers provide Class 1 eye safety by design. Agilent Technologies has tested the transceiver design for compliance with the requirements listed in Table 1: Regulatory Compliance, under normal operating conditions and under a single-fault condition.
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Table 1. Regulatory Compliance Feature Electrostatic Discharge (ESD) to the Electrical Pins Electrostatic Discharge (ESD) to the Duplex LC Receptacle Electromagnetic Interference (EMI) Test Method MIL-STD-883C Method 3015.4 Variation of IEC 61000-4-2 Performance Class 2 (2000-3999 Volts) Typically withstand at least 25 kV without damage when the duplex LC connector receptacle is contacted by a Human Body Model probe. System margins are dependent on customer board and chassis design.
Immunity
FCC Class B CENELEC EN55022 Class B (CISPR 22A) VCCI Class 1 Variation of IEC 61000-4-3
Eye Safety
Component Recognition
US FDA CDRH AEL Class 1 EN(IEC)60825-1,2, EN60950 Class 1 Underwriters Laboratories and UL file # E173874 Canadian Standards Association Joint Component Recognition for Information Technology Equipment including Electrical Business Equipment.
Typically shows a negligible effect from a 10 V/m field swept from 80 to 1000 MHz applied to the transceiver without a chassis enclosure. CDRH file # 9720151-13 TUV file # R2079009.51
Note: 1. Changes to IEC 60825-1,2 are currently anticipated to allow higher eye-safe Optical Output Power levels. Agilent may choose to take advantage of these in future revisions to this part.
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1 H VCCT,R 10 F 0.1 F 1 H CHASSIS GROUND
*RES
VCCT 0.1 F *RES
AGILENT HFBR-5730L
GP04 TX_FAULT VREFR TX[0:9] TBC EWRAP SYNC LOOP SO1+ SO1- 50 50 C C
TX_DISABLE TX_FAULT TD+ R TD- VEET VCCR LASER DRIVER & EYE SAFETY CIRCUITRY
MAC ASIC
RBC RX_RATE
AGILENT HDMP-1687
RX[0:9] SYN1 RC1(0:1) RCM0 RFCT SI1+ R SI1- VCCT,R *RES *RES *RES 50 50
10 F
0.1 F
RD+ C C RD- AMPLIFICATION & QUANTIZATION
RX_LOS
REF_RATE *RES RX_LOS MOD_DEF2 MOD_DEF1 MOD_DEF0 VEER NOTE: * 4.7 k < RES < 10 k EEPROM
GPIO(X) GPIO(X) GP14 REFCLK 106.25 MHz
Figure 4. Typical application configuration.
1 H VCCT 0.1 F
1 H VCCR 0.1 F 10 F 0.1 F 10 F 3.3 V
SFP MODULE
HOST BOARD
NOTE: INDUCTORS MUST HAVE LESS THAN 1 SERIES RESISTANCE PER MSA.
Figure 5. MSA recommended power supply filter.
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Table 2. Pin Description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Name VEE T TX Fault TX Disable MOD-DEF2 MOD-DEF1 MOD-DEF0 Rate Select LOS VEE R VEE R VEE R RD- RD+ VEE R VCCR VCCT VEE T TD+ TD- VEE T Function/Description Transmitter Ground Transmitter Fault Indication - High indicates a fault Transmitter Disable - Module disables on high or open Module Definition 2 - Two-wire serial ID interface Module Definition 1 - Two-wire serial ID interface Module Definition 0 - Grounded in module Not Connected Loss of Signal - High indicates loss of signal Receiver Ground Receiver Ground Receiver Ground Inverse Received Data Out Received Data Out Receiver Ground Receiver Power - 3.3 V 5% Transmitter Power - 3.3 V 5% Transmitter Ground Transmitter Data In Inverse Transmitter Data In Transmitter Ground MSA Notes 1 2 3 3 3 4
5 5 6 6 7 7
Notes: 1. TX Fault is an open collector/drain output, which should be pulled up externally with a 4.7K - 10 K resistor on the host board to a supply < VCC T+0.3 V or VCCR+0.3 V. When high, this output indicates a laser fault of some kind. Low indicates normal operation. In the low state, the output will be pulled to < 0.8 V. 2. TX Disable is an input that is used to shut down the laser output per the state table below. It is pulled up within the module with a 4.7K - 10 K resistor. Low (0 - 0.8 V): Transmitter on Between (0.8 V and 2.0 V): Undefined High (2.0 - 3.465 V): Transmitter Disabled Open: Transmitter Disabled 3. Mod-Def 0,1,2. These are the module definition pins. They should be pulled up with a 4.7-10 K resistor on the host board to a supply less than VCCT + 0.3 V or VCC R + 0.3 V. Mod-Def 0 is grounded by the Module to indicate that the module is present Mod-Def 1 is clock line of two-wire serial interface for optional serial ID Mod-Def 2 is data line of two-wire serial interface for optional serial ID 4. LOS (Loss of Signal) is an open collector/drain output that should be pulled up externally with a 4.7K - 10 K resistor on the host board to a supply < VCC T,R+0.3 V. When high, this output indicates the received optical power is below the worst case receiver sensitivity. Low indicates normal operation. In the low state, the output will be pulled to < 0.8 V. 5. RD-/+: These are the differential receiver outputs. They are AC coupled 100 differential lines which should be terminated with 100 differential at the user SerDes. The AC coupling is done inside the module and is thus not required on the host board. The voltage swing on these lines will be between 400 and 2000 mV differential (200 - 1000 mV single ended) when properly terminated. These levels are compatible with CML and LVPECL voltage swings. 6. VCC R and VCCT are the receiver and transmitter power supplies. They are defined as 3.3 V 5% at the SFP connector pin. The associated in-rush power supply current will typically be no more than 30 mA above the steady state supply current after 500 nanoseconds. 7. TD-/+: These are the differential transmitter inputs. They are AC coupled differential lines with 100 differential termination inside the module. The AC coupling is done inside the module and is thus not required on the host board. The inputs will accept differential swings of 400 - 2400 mV (200 - 1200 mV single ended), however the recommended differential voltage swing is found in Table 6. These levels are compatible with CML and LVPECL voltage swings.
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Table 3. Absolute Maximum Ratings Parameter Storage Temperature Case Temperature Relative Humidity Module Supply Voltage Data/Control Input Voltage Sense Output Current - LOS,TX Fault MOD DEF2 Symbol TS TC RH VCCT,R VI ID ID Minimum -40 -40 5 -0.5 -0.5 Typical Maximum 100 85 95 3.6 VCC 150 5 Unit C C % V V mA mA Notes 1 1, 2 1 1, 2 1 1 1
Notes: 1. Absolute Maximum Ratings are those values beyond which damage to the device may occur if these limits are exceeded for other than a short period of time. See Reliability Data Sheets for specific reliability performance. 2. Between Absolute Maximum Ratings and the Recommended Operating Conditions, functional performance is not intended, device reliability is not implied, and damage to the device may occur over an extended period of time.
Table 4. Recommended Operating Conditions Parameter Case Temperature Module Supply Voltage Data Rate Symbol TC VCCT,R Minimum 0 3.135 Typical 3.3 1.0625 Maximum 70 3.465 Unit C V Gb/s Notes 1 1 1
Notes: 1. Recommended operating conditions are those values outside of which functional performance is not intended, device reliability is not implied, and damage to the device may occur over an extended period of time. See Reliability Data Sheet for specific reliability performance.
Table 5. Transceiver Electrical Characteristics (TC = 0C to 70C, VCCT,R = 3.3 V 5%) Parameter AC Electrical Characteristics Power Supply Noise Rejection (Peak-to-Peak) DC Electrical Characteristics Module Supply Current Power Dissipation Sense Outputs: Transmit Fault (TX_FAULT), Loss of Signal (LOS), MOD-DEF2 Control Inputs: Transmitter Disable (TX_DISABLE), MOD-DEF1,2 Symbol PSNR Minimum Typical 100 Maximum Unit mV Notes 1
ICC PDISS VOH VOL VIH VIL 2.0 0.0 2.0 0.0
160 530
220 765 VCCT,R + 0.3 0.8 VCC 0.8
mA mW V V V V 2 2 2 2
Notes: 1. MSA filter is required on host board 10 Hz to 2 MHz. 2. LVTTL, external 4.7-10 K pull-up resistor required.
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Table 6. Transmitter and Receiver Electrical Characteristics (TC = 0C to 70C, VCCT,R = 3.3 V 5%) Parameter Data Input: Transmitter Differential Input Voltage (TD +/-) Data Output: Receiver Differential Output Voltage (RD +/-) Contributed Total Jitter (Receiver) 1.0625 Gb/s Deterministic Jitter (Receiver) 1.0625 Gb/s Receive Data Rise & Fall Times (Receiver) Symbol VI Minimum 400 Typical Maximum 2000 Unit mV Notes 1
VO TJ DJ Trf
400
1500
2000 205 0.218 113 0.12 350
mV ps UI ps UI ps
2
3
Notes: 1. Internally AC coupled and terminated (100 Ohm differential). These levels are compatible with CML and LVPECL voltage swings. 2. Internally AC coupled with an external 100 Ohm differential load termination. 3. 20%-80% Rise & Fall times measured with a 500 MHz signal utilizing a 1010 data pattern.
Table 7. Transmitter Optical Characteristics (TC = 0C to 70C, VCCT,R = 3.3 V 5%) Parameter Output Optical Power (Average) Symbol POUT Minimum -10 Typical Maximum 0 Unit dBm Notes 50/125 m NA = 0.2 Note 1 62.5/125 m NA = 0.275 Note 1 2 FC-PI Std FC-PI Std FC-PI Std 20%-80%, FC-PI Std FC-PI Std
POUT
-10
0
dBm
Optical Extinction Ratio Optical Modulation Amplitude (Peak-to-Peak) 1.0625 Gb/s Center Wavelength Spectal Width - rms Optical Rise /Fall Time RIN12 (OMA), maximum Contributed Total Jitter (Transmitter) 1.0625 Gb/s Deterministic Jitter (Receiver) 1.0625 Gb/s POUT TX_DISABLE Asserted
ER OMA C Trise/fall RIN TJ DJ POFF
9 156 830 860 1.0 300 -116 0.267 252 85 0.09 -35
dB W nm nm ps dB/Hz UI ps ps UI dBm
Notes: 1. Max POUT is the lesser of 0 dBm or maximum allowable per Eye Safety Standard. 2. Required for compliance to FC-PH-2.
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Table 8. Receiver Optical Characteristics (TC = 0C to 70C, VCCT,R = 3.3 V 5%) Parameter Optical Power Min Optical Modulation Amplitude (Peak-to-Peak) 1.0625 Gb/s Stressed Receiver Sensitivity (OMA) 1.0625 Gb/s Symbol PIN OMA Minimum -17 31 Typical Maximum 0 Unit dBm W Notes FC-PI Std, 1 FC-PI Std, 2
55 67
W W dB dBm dBm dB
Return Loss Loss of Signal - Assert Loss of Signal - De-assert Loss of Signal Hysteresis
PA PD PD - P A
12 -31 0.5
-17.5 -17.0 5
50 m fiber, FC-PI Std 62.5 m fiber, FC-PI Std FC-PI Std 4 4
Notes: 1. Required for compliance to FC-PH-2. 2. An OMA of 31 is approximately equal to an average power of -17 dBm assuming an Extinction Ratio of 9 dB. Sensitivity measurements are made at eye center with BER = 10E-12. 3. 1.0625 Gb/s stressed receiver vertical eye closure penalty (ISI) minimum is 0.96 dB for 50 m fiber and 2.18 dB for 62.5 m fiber. Stressed receiver DCD component minimum (at TX) is 80 ps. 4. These average power values are specified with an Extinction Ratio of 9 dB. The Loss of Signal circuitry responds to OMA (peak-to-peak) power, not to average power.
Table 9. Transceiver Timing Characteristics (TC = 0C to 70C, VCCT,R = 3.3 V 5%) Parameter TX Disable Assert Time TX Disable Negate Time Time to Initialize, including Reset of TX_FAULT TX Fault Assert Time TX Disable to Reset LOS Assert Time LOS De-assert Time Serial ID Clock Rate Symbol t_off t_on t_init t_fault t_reset t_loss_on t_loss_off F_serial_clock Minimum Typical Maximum 10 1 300 100 10 100 100 100 Unit s ms ms s s s s kHz Notes 1 2 3 4 5 6 7
Notes: 1. Time from rising edge of TX Disable to when the optical output falls below 10% of nominal. 2. Time from falling edge of TX Disable to when the modulated optical output rises above 90% of nominal. 3. From power on or negation of TX Fault using TX Disable. 4. Time from fault to TX fault on. 5. Time TX Disable must be held high to reset TX_FAULT. 6. Time from LOS state to RX LOS assert per Figure 6. 7. Time from non-LOS state to RX LOS de-assert per Figure 6.
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VCC > 3.15 V Tx_FAULT Tx_DISABLE TRANSMITTED SIGNAL t_init
VCC > 3.15 V Tx_FAULT Tx_DISABLE TRANSMITTED SIGNAL t_init
t-init: TX DISABLE NEGATED
t-init: TX DISABLE ASSERTED
VCC > 3.15 V Tx_FAULT Tx_DISABLE TRANSMITTED SIGNAL
Tx_FAULT Tx_DISABLE TRANSMITTED SIGNAL t_off t_init t_on
INSERTION
t-init: TX DISABLE NEGATED, MODULE HOT PLUGGED
t-off & t-on: TX DISABLE ASSERTED THEN NEGATED
OCCURANCE OF FAULT Tx_FAULT Tx_DISABLE TRANSMITTED SIGNAL t_fault
OCCURANCE OF FAULT Tx_FAULT Tx_DISABLE TRANSMITTED SIGNAL
* SFP SHALL CLEAR TX_FAULT IN < t_init IF THE FAILURE IS TRANSIENT
t_reset
t_init*
t-fault: TX FAULT ASSERTED, TX SIGNAL NOT RECOVERED
t-reset: TX DISABLE ASSERTED THEN NEGATED, TX SIGNAL RECOVERED
OCCURANCE OF FAULT Tx_FAULT Tx_DISABLE TRANSMITTED SIGNAL
t_fault2
OPTICAL SIGNAL LOS
t_reset
OCCURANCE OF LOSS
t_loss_on
t_loss_off
* SFP SHALL CLEAR TX_FAULT IN < t_init IF THE FAILURE IS TRANSIENT
t_init*
t-fault2: TX DISABLE ASSERTED THEN NEGATED, TX SIGNAL NOT RECOVERED NOTE: t_fault2 typical 1.7 to 2.0 ms.
t-loss-on & t-loss-off
Figure 6. Transceiver timing diagrams (module installed except where noted).
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Table 10. EEPROM Serial ID Memory Contents Address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Hex 03 04 07 00 00 00 00 20 40 0C 01 01 0B 00 00 00 32 1E 00 00 41 47 49 4C 45 4E 54 20 20 20 20 20 20 20 20 20 00 00 30 D3 ASCII Address 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 Hex 48 46 42 52 2D 35 37 33 30 4C 20 20 20 20 20 20 20 20 20 20 00 00 00 Note 3 00 1A 00 00 ASCII H F B R - 5 7 3 0 L Address 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 Hex Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 20 20 00 00 00 Note 3 ASCII Address 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 Hex ASCII
A G I L E N T
Notes: 1. Address 61-83 specify a unique identifier. 2. Address 84-91 specify the date code. 3. Addresses 63 and 95 are check sums. Address 63 is the check sum for bytes 0-62 and address 95 is the check sum for bytes 64-94.
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AGILENT HFBR-5730L 850 nm LASER PROD 21CFR(J) CLASS 1 COUNTRY OF ORIGIN YYWW XXXXXX
13.40 0.1 (0.53 0.004)
13.75 0.1 (0.54 0.004)
56.40 0.2 (2.22 0.01)
SEE DETAIL 1
TCASE REFERENCE POINT
AREA FOR PROCESS PLUG
13.0 0.1 (0.51 0.004)
14.8 MAX. UNCOMPRESSED (0.58)
14.20 0.1 (0.56 0.004) DETAIL 1 SCALE 2x
0.7 MAX. UNCOMPRESSED (0.03)
FRONT EDGE OF SFP TRANSCEIVER CAGE
6.25 0.05 (0.25 0.002)
8.50 0.1 (0.33 0.004)
11.80 0.2 (0.46 0.008)
DIMENSIONS ARE IN MILLIMETERS (INCHES)
TX
RX
Figure 7a. Module drawing.
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1.7 0.9 (0.07 0.04) 3.5 0.3 (0.14 0.01) 41.73 0.5 (1.64 0.02)
PCB
BEZEL
15 MAX. (0.59)
AREA FOR PROCESS PLUG
CAGE ASSEMBLY 15.25 0.1 (0.60 0.004) 11 REF. (0.43) 9.8 MAX. (0.39) 1.5 REF. (0.06) BELOW PCB 10 REF (0.39) TO PCB 0.4 0.1 (0.02 0.004) BELOW PCB 10.4 0.1 (0.41 0.004)
16.25 0.1 MIN. PITCH (0.64 0.004)
MSA-SPECIFIED BEZEL
DIMENSIONS ARE IN MILLIMETERS (INCHES).
Figure 7b. Assembly drawing.
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Y
X 34.5 10 3x 10x 1.05 0.1 0.1 L X A S 1 B 7.2 2.5 2.5 7.1 0.85 0.05 0.1 S X Y A 1 3.68
16.25 MIN. PITCH PCB EDGE
5.68 8.58 11.08 16.25 14.25 REF.
PIN 1
20
2x 1.7
8.48 9.6 11.93
10
11
4.8
SEE DETAIL 1 11x 2.0 11x 2.0 26.8 3 41.3 42.3 10 3x 5 9x 0.95 0.05 0.1 L X A S 2
5 3.2 0.9 20x 0.5 0.03 0.06 S A S B S
PIN 1
20
NOTES: 10.53 11.93 1.PADS AND VIAS ARE CHASSIS GROUND. 2.THROUGH HOLES, PLATING OPTIONAL.
10.93 9.6 0.8 TYP.
11 10
3.HATCHED AREA DENOTES COMPONENT AND TRACE KEEPOUT (EXCEPT CHASSIS GROUND). 4.AREA DENOTES COMPONENT KEEPOUT (TRACES ALLOWED). DIMENSIONS ARE IN MILLIMETERS
4 2x 1.55 0.05 0.1 L A S B S DETAIL 1 2 0.05 TYP. 0.06 L A S B S
Figure 7c. SFP host board mechanical layout.
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www.agilent.com/semiconductors
For product information and a complete list of distributors, please go to our web site. For technical assistance call: Americas/Canada: +1 (800) 235-0312 or (408) 654-8675 Europe: +49 (0) 6441 92460 China: 10800 650 0017 Hong Kong: (+65) 6271 2451 India, Australia, New Zealand: (+65) 6271 2394 Japan: (+81 3) 3335-8152(Domestic/International), or 0120-61-1280(Domestic Only) Korea: (+65) 6271 2194 Malaysia, Singapore: (+65) 6271 2054 Taiwan: (+65) 6271 2654 Data subject to change. Copyright (c) 2002 Agilent Technologies, Inc. Obsoletes 5988-3384EN July 15, 2002 5988-7282EN

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